Bit-error rate improvement of TLC NAND Flash using state re-ordering
نویسندگان
چکیده
منابع مشابه
Bit-error rate improvement of TLC NAND Flash using state re-ordering
In scaled technologies, large cell-to-cell interference and FN tunneling disturbance degrade threshold voltage (Vt) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P1 ~ P7) in the narrow Vt window, incurring large biterror rate (BER). In this paper, we propose a state re-ordering technique to increase the efficienc...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2012
ISSN: 1349-2543
DOI: 10.1587/elex.9.1775